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2002 Microchip Technology Inc.

Preliminary

DS30485A-page 123

PIC18FXX39

15.0 PULSE WIDTH MODULATION

(PWM) MODULES

PIC18FXX39 devices are equipped with two 10-bit

PWM modules. Each contains a register pair

(CCPxH:CCPxL), which operates as a Master/Slave

Duty Cycle register, and a control register (CCPxCON).

The modules use Timer2 (Section 12.0) as their time-

base reference. Figure 15-1 shows a simplified block

diagram of the module’s operation.

This section gives a brief overview of PWM operation

controlled

the

Motor

Control

module

(Section 14.0). Operation is described with respect to

PWM1, but is equally applicable to PWM2.

15.1

PWM Mode

In Pulse Width Modulation, each PWM pin produces a

PWM output with a resolution of up to 10 bits.

A PWM output (Figure 15-2) has a time-base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 15-1:

SIMPLIFIED PWM BLOCK

DIAGRAM

FIGURE 15-2:

PWM OUTPUT

15.1.1

PWM PERIOD

The PWM period is specified when the Motor Control

module is initialized. The PWM period can be

calculated using the formula:

PWM period = [(PR2) + 1] 4 TOSC

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

The API method void ProMPT_Init (page 118)

sets the required PWM frequency in the application.

The parameter PWMfrequency determines the operat-

ing frequency of the module. When it is ‘0’, the PWM

frequency set in the Motor Control module is 9.75 kHz;

when it is ‘1’, the set PWM frequency is 19.53 kHz.

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

TMR2 is cleared

The PWM1 pin is set (exception: if PWM duty

cycle = 0%, the PWM1 pin will not be set)

The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note:

The PWM modules are used exclusively

by the Motor Control module. As such, they

are not available to users as a separate

resource. Although their locations are

shown on the device data memory maps,

users should not modify the values of

these registers.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer,

PWM1 pin and

latch Duty Cycle

PWM1

Note 1: 8-bit timer is concatenated with 2-bit internal Q

clock, or 2 bits of the prescaler to create a

10-bit time-base.

Note:

The Timer2 postscaler (see Section 12.0)

is not used in the determination of the

PWM frequency. The postscaler could be

used to have a servo update rate at a

different frequency than the PWM output.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

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